We help you achieve high-speed, low-power working silicon in three ways:
Micro Magic tools provide fully integrated design flow management, graphical design entry, datapath and memory compilers, and the world's fastest SoC layout editing and viewing system with realtime DRC. If you're doing 3D design (stacked) or interposer design, the MMI MAX-3D Design Suite is the only toolset designed from bottom up to be fully 3D aware.
SUE SoC Design Manager
Everything needed to manage today's SoC Design Flow
SUE combines Verilog, Schematic Capture, Documentation, Timing and Simulation tools to plan and manage your SoC project.
DPC for Datapaths
Faster, Smaller, Lower Power, Easier routing
Micro Magic's DPC Datapath Compiler can place, route and time 100K gates/min. DPC will analyze congestion, and generates a custom-like bit-slice placement to improve timing and routing.
MAX-3D Path Finder
Quickly and Automatically evaluate viability of 3D
Path Finder helps determine whether 3D TSV wafer stack is the best solution for your project. Use MAX-3D Path Finder to analyze partitioning, extract and simulate 3D nets, and generally explore the viability of an interposer or stacked-die implementation.
The tool for true 3-Dimensional Layout
Load multilple chips/wafers and maintain distinct tech files for each layer. Full-featured editing for each tech file with real-time redisplay.
MAX-3D TSV Placer
Automatic TSV Location, Optimization and Placement
MAX-3D TSV Placer scans your multi-level layout for optimal legal TSV placement. You can also adjust layout and insert blocking layers to modify placements if required.
The tool for chip/package co-design.
MAX-3D System enables you to view, edit and analyze multiple wafers/layers of one chip stack up thru the package and across the board to another chip stack.
MMI provides tools for all aspects of IC layout and design including specialized tools for Datapath Design, SoC Design Management and a powerful, specialized program for memories and other regular structures, MCC - Megacell Compiler.