Micro Magic, Inc. DPC-Datapaths + SUE SoC Design Manager
Faster, Smaller, Lower Power
Use DPC to make your datapaths faster, smaller, lower power, easier to route.
Greater Design Control
HOW DPC SOLVES THE POWER/ PERFORMANCE PROBLEM:
- Import design data using schematics or Verilog.
- Creates custom-like bit-slice placement which reduces congestion and improves routing.
- Performs postplacement timing analysis.
- Computes critical paths and provides timing information at each node.
- Auto-sizes gates based on your constraints (optimizing for timing and power, or power alone).
- Modify your design and see the new results very quickly. Iterations are done in minutes – DPC computes 100,000 gates per minute.
- Checks for “hot spots” with congestion analysis.
- Outputs a DEF placement file for your existing P&R flow.
- Verifes timing postroute, and shows results graphically.
Left:Standard ASIC flow is a “black box” providing little information. Iterations take days/weeks.
Right: DPC flow provides timing feedback early in the design process. Iterations take seconds/ minutes.
Top Left:Verilog or Schematics to enter design information.
Lower Left:
CRITICAL PATH ANALYSIS
DPC computes placement, route, and timing information.
Top Right:Critical paths are displayed on the schematic and placement views.
Control Your Placement
DPC gives the designer complete control of the datapath. You control relative placement of gates, and you can designate exact placement for specific gates.
Control Your Gate Sizing
DPC automatically sizes the gates in your datapath, using a production-proven algorithm to select optimal sizes for speed, power or both. Using the “power down” option, Auto- Sizer will only down-size gates in order to minimize power required. At your option, you can also manually resize gates.
Timing Information and Critical-Path Analysis
DPC provides immediate timing feedback for placement and gate sizing. Multiple what-if experiments can be performed in seconds. Using a graphical display that back annotates timing to the schematic and placement file, you can easily identify timing problems and rapidly iterate through solutions. DPC is so fast it can place, route, and time a 100,000 gate datapath in one minute.
Design Inputs.
DPC reads your Verilog and produces a schematic. For designers who don’t use schematics, there is a “Verilog- Only” option. Once you are meeting your timing and power goals, you can use the built-in congestion analyzer to check for hot spots. Due to the regular bitslice placement and congestion check, DPC blocks usually route correctly on the first pass.
A DEF placement file and the Verilog netlist is sent to your router.
- Everything needed to manage today's SoC Design Flow
SUE SoC Design Manager Flow
The Framework for All Design Capture, Simulation, Timing and Data Management
Manage Cirsuits, Verilog, Documentation and Version Control
Fast and Effective Schematic Capture Tool
Supports Industry Standard File Formats
Drives Most Verilog and SPICE Simulators
Manage Your Design with SUE
SUE combines schematic capture and verification with control of Verilog blocks, timing models, standard cell libraries and documentation. SUE is useful from an architectural level to plan your design, and manage the design process.
- Provides an architectural overview of your design.
- Fully hierarchical, SUE can drill down to gate-level or transistor level detail of any block.
- Structural Verilog is imported and automatically arranged as a schematic.
- Enter your designs quickly with the simple graphical user interface.