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Micro Magic tools offer improved 3D performance.
 NEW! 3D Path Finder & TSV Placer -More Info -

NAX-3D TSV/PATHFINDER SUITE

The world's first truly 3-D aware layout editor

MAX-3D Layout Editor MAX-3D is the only true 3D layout editor, handling multiple technologies with true Through-Via capability

Enabling 'Through-Silicon Via Wafer Stack' Technology a technology allowing faster interconnects between discrete wafers. This is accomplished by connecting wafers of varying technologies together with vias through the wafers yielding a single 3-D stacked chip.

Click for MAX Datasheet

50X faster, with schematic-driven layout

MAX Layout Editor comes with continuous DRC, connectivity tracing, schematic cross-probing, wiring tool, extraction, schematic-driven layout, and more.

MAX-LS Layout System seamlessly integrates the schematic capture of SUE with the MAX layout editor to provide true, schematic-driven physical layout. It includes interactive cell generation based on LVS and DRC correct layout, and can handle the largest SoC IC design databases. Its GDSII output can go directly to mask composition products for IC fabrication.

 

MAX-3D Design Suite

NEW!   MAX-3D Path Finder
MAX-3D TSV Placer !

Based on MAX-3D Layout Editor


Our advanced IC Design solutions producing full custom performance
with ASIC effort.

Micro Magic tools interface easily with common Point Tools DPC DataPath Compiler  - Click for Datasheet SUE Design Manager  - Click for Datasheet MAX Layout Environment  - Click for Datasheet MCC MegaCell Compiler - Click for Datasheet DPC DEF file compatible with standard routers SUE has built-in interfaces to several Verilog Simulators SUE and MAX generate standard formats supporting LVS tools MAX has built-in DRC, and cal also run Calibre. MCC can directly output Verilog netlists DPC has built-in Timing as well as interfaces to PrimeTime and Pathmill SUE has a direct HSPICE interface for quick Circuit SimulationSUE to LVA Both SUE and MAX read and netlist to standard place-n-route tools MCC outputs SPICE netlist and has a built-in waveform viewer

Mouse over blue boxes to
learn how Micro Magic tools
work with Point Tools
(JavaScript)

All Micro Magic tools are fully documented,
and include an interactive, on-line tutorial.


Gives 3X better performance than ASIC.

The Datapath Compiler generates data paths from a schematic view and back-annotates accurate timing information onto the schematic in seconds. It can place custom-style "bit-slice" data paths, minimizing wire lengths for high performance, and can even include control logic, all using an existing standard cell library.

Click to View SUE Datasheet

Controls your point tools.

SUE Design Manager is a graphical environment that allows users to enter, visualize, and control large, complex chip designs. It is the first tool to combine HDL-based functional designs with structural design. This tool understands everything from Verilog to the operation and physical placement of transistors and wires.

Click for MCC Datasheet

Design, build and analyze custom memories

The MegaCell Compiler allows users to easily build their own generators for SRAMs, DRAMs, ROMs, pad rings, or any other regular or semi-regular structure, in just minutes. Verilog, HSPICE, critical path netlists, and timing models can all be generated automatically.

 

Load and view your largest designs

MAX-View Layout Viewer lets you load and view any size layout, in REAL TIME. MAX-View imports GDSII and .max files, as well as other industry standard technology files. Customize layer display settings; push, pop, and view cell internals; explore cell hierarchy and connectivity tracing -- all with instantaneous re-display.

 

 

 

 

     
 
     
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 Micro Magic, Inc.
 408.414.7647
 Sunnyvale, CA

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