The world's first truly 3-D aware layout editor
MAX-3D Layout Editor MAX-3D is the only true 3D layout editor, handling multiple technologies with true Through-Via capability
Enabling 'Through-Silicon Via Wafer Stack' Technology a technology allowing faster interconnects between discrete wafers. This is accomplished by connecting wafers of varying technologies together with vias through the wafers yielding a single 3-D stacked chip.
50X faster, with schematic-driven layout
MAX Layout Editor comes with continuous DRC, connectivity tracing, schematic cross-probing, wiring tool, extraction, schematic-driven layout, and more.
MAX-LS Layout System seamlessly integrates the schematic capture of SUE with the MAX layout editor to provide true, schematic-driven physical layout. It includes interactive cell generation based on LVS and DRC correct layout, and can handle the largest SoC IC design databases. Its GDSII output can go directly to mask composition products for IC fabrication.
NEW! MAX-3D Path Finder
MAX-3D TSV Placer
Based on MAX-3D Layout Editor
Our advanced IC Design solutions producing full custom performance
with ASIC effort.
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work with Point Tools
All Micro Magic tools are fully documented,
and include an interactive, on-line tutorial.
Gives 3X better performance than ASIC.
The Datapath Compiler generates data paths from a schematic view and back-annotates accurate timing information onto the schematic in seconds. It can place custom-style "bit-slice" data paths, minimizing wire lengths for high performance, and can even include control logic, all using an existing standard cell library.
Controls your point tools.
SUE Design Manager is a graphical environment that allows users to enter, visualize, and control large, complex chip designs. It is the first tool to combine HDL-based functional designs with structural design. This tool understands everything from Verilog to the operation and physical placement of transistors and wires.
Design, build and analyze custom memories
The MegaCell Compiler allows users to easily build their own generators for SRAMs, DRAMs, ROMs, pad rings, or any other regular or semi-regular structure, in just minutes. Verilog, HSPICE, critical path netlists, and timing models can all be generated automatically.